Scalable path towards 3D integration of superconducting qubits using advanced 300mm foundry manufacturing capabilities

Error-corrected quantum processors of the future will require a large number of connected physical qubits to encode logical qubits for practical quantum computation. Superconducting qubits have emerged as prime contenders for implementing such quantum processors. Error-correction codes, such as the surface code, require these qubits to be arranged in repeated 2D lattices on a chip, which presents challenges for qubit addressability in terms of peripheral wiring and the fan-out of their control and readout signals. To circumvent these 2D wiring challenges, heterogeneous 3D integration is essential. Here, the qubit chip can be separated from its readout and control elements using superconducting flip-chip bonding techniques, and the signals can be efficiently routed to the qubits using superconducting through-silicon vias (TSVs) from a separate readout chip. We will present our efforts in combining 3D integration modules, such as bumps, spacers, and TSVs, with superconducting qubits and resonators using advanced CMOS processing techniques on 300mm wafers. Preliminary measurements of the impact of 3D integration modules on qubits and resonators will be discussed.