Effects of Charge Traps on Electronic Transport in 2D WSe₂ Field-Effect Transistors

Atomically thin layer transition metal dichalcogenides (TMDs) are structurally ideal channel materials to design the ultimate atomic electronics after the silicon era. However, the charge transport in atomically thin (monolayer, bilayer, and trilayer) TMDs-based field-effect transistors (FETs) devices are strongly influenced by charge traps originating from an intimate environment. Therefore, to analyze the impact of charge traps on the intrinsic nature of charge transport behavior in different thicknesses WSe₂ devices, we performed temperature-dependent electrical transport measurements of different thicknesses WSe₂ devices (monolayer to multilayer). Different thicknesses of WSe₂-based FETs show different charge transport regimes in the insulating region and metal-insulator transition (MIT) at higher temperatures. The obtained conductivity results suggest the intermediate tunneling-hopping transport coexists in the insulating regime at low temperatures. The hopping parameter T_o and localized length significantly vary with the thickness of the WSe₂ flake, indicating the different disorder landscapes forms with reducing channel thickness. While at high temperatures, the insulating nature of the system changes into metallic, where the conductivity is reduced with increasing temperature.