Reduced Disorder and Opportunities for Scalable, 2-Dimensional Gate Array Design Using the SLEDGE Architecture in Si/SiGe Exchange-Only Qubits

The recently-demonstrated Single-Layer Etch-Defined Gate-Electrode (SLEDGE) architecture in Si/SiGe exchange-only qubits enables flexible device design and fabrication by separating the front-end-of-line (FEOL) gate stack from the back-end-of-line (BEOL) interconnects [1]. For FEOL gates, moving from a lift-off to subtractive fabrication process with improved gate stack cleans decreases electrostatic disorder; we measure Hall bars with a reduced minimum electron density at which conduction occurs and quantum dot device gates with reduced variability in voltages at which electrons load and tunnel. BEOL routing enables scalable, 2-dimensional gate array designs of the FEOL, instead of 1-dimensional arrays or ring-like designs, but requires good electrical connections between vias and gates. We show that if a via is poorly-connected to a gate, the gate behaves as an unwanted quantum dot (coined “parasitic metal dot,” PMD). With design and fabrication improvements, we measure drastically reduced PMD prevalence. We further show SLEDGE devices can be used for coherent operation of high-performance qubits.

 

[1] Ha et al. arXiv:2107.10916