Roughness of Si/SiO₂ interface and its impact on CMOS spin qubits

Quantum computing has the potential to be world changing due to its promise to tackle problems currently intractable to even the most advanced present day supercomputer.  The leading technology uses superconducting transmon qubits  with an overall effective qubit count of 53. However, a 1-million-plus physical qubit processor is required to make quantum computers useful for the most notable applications. To achieve this, scalability and operating temperature may well become a significant challenge for superconducting qubits. On the other hand, silicon qubits, which are much smaller than transmons and able to work at higher temperatures [1,2] emerge as a viable candidate for large-scale quantum processing. The prospect of leveraging the multi-trillion dollar complementary-MOS (CMOS) manufacturing industry is a very strong motivator for the development of silicon-CMOS-based quantum computing.  However, it remains unknown what will be the impact of the defects on the oxide layer in CMOS devices that are fabricated to host quantum dots spin qubits.  In this talk we will explore how the roughness in the Si/SiO2 interface impacts silicon-based CMOS qubits by utilising atomistic multiband tight-binding for single electron quantum dots and path integral Monte Carlo (PIMC) for electron interactions. 

[1] C. H. Yang et al., Nature 580, 505 (2020).  

[2] L. Petit et al., Nature 580, 355 (2020).