Scalable architecture for next generation superconducting quantum processors

We discuss a new architecture for superconducting qubits which uses multilevel wiring built off of advanced packaging techniques such as indium bump bonds and through-silicon vias. This architecture improves the scalability of quantum processor design by simplifying I/O routing and reducing crosstalk without sacrificing qubit coherence. Measurement results of a 6-qubit demonstrator chip will be reported, including qubit coherence, pair-wise qubit gate performance and characterization of the individual packaging elements used in the structure.