Opportunities and Challenges at the Edge of Scaling in Advanced Memory and Foundry Technologies

As DRAM scaling approaches the vicinity of the 10nm design rule, physical and process limitations are increasingly constraining further pitch shrink. In this context, vertically stacked DRAM architectures, commonly referred to as 3D DRAM, are emerging as potential candidates for the next generation of memory technology. Unlike conventional planar DRAM, 3D DRAM features horizontally arranged Si channels and capacitors, increasing bit density by stacking layers within the same 2D layout—similar in principle to 3D NAND. In the logic domain, a significant structural evolution is also anticipated. The 3D stacked FET, also referred to as a complementary FET (cFET), vertically integrates NMOS and PMOS transistors and offers a promising path to extend density beyond what is achievable in today's planar CMOS structures. As the industry shifts from 2D scaling to 3D integration, the importance of advanced plasma etching processes has never been greater. Advanced etching is becoming essential in both 3D DRAM and the 3D stacked FET, as each demands precise etching of silicon materials in high aspect ratio (HAR) structures. Unlike traditional HAR etching—used in DRAM capacitors or 3D NAND channels—which typically involves dielectric etching with CCP systems, the emerging processes now demand HAR Si or SiGe etching using ICP systems. This convergence highlights a common technological challenge across both memory and logic: enabling next-generation devices through advanced silicon etching. This presentation reviews the key plasma etch processes required for future DRAM and logic devices, assesses the current technological gaps, and discusses critical research directions. It also considers equipment-related cost and performance trade-offs, emphasizing the need for investment and innovation to meet integration demands. While past generations of DRAM and logic scaled through steady evolution of conventional process technologies, the move toward 3D DRAM and the 3D stacked FET necessitates a more disruptive approach. By advancing core plasma etching capabilities today, we aim to build the foundation for the high-density, high-performance semiconductors required by tomorrow's IT systems.