Challenges and solutions for fine pitch high aspect ratio patterning in sub-10nm DRAM device

High aspect ratio contact (HARC) etching for the capacitor patterning in DRAM is the critical process which can determine the extendibility of conventional scheme for the sub-10nm design rule device. Not only the aspect ratio dependent etch rate retarding in the small holes but also the abrupt mask erosion rate increases are serious obstacles to be overcome when shrinking the pitch size. Various technologies have been brought up in HARC etching history to solve the tradeoff between mask selectivity and loading effect. In this talk, the path finding techniques including new material adoption, multi-level pulsing and local uniformity control methods will be introduced to overcome the limitation of the fine pitch HARC patterning for the next generation devices.