Material Modification and Selective Removal Process for incoming logic and memory device

The semiconductor industry is facing severe changes and serious technical challenges. DRAM is moving into 3D or 4F2 vertical structures. NAND keeps increasing more multi-layers using two or more than three tiers. The logic device is moving into the gate-all-around transistor type. The material modification and selective removal process for logic and memory devices requires very precise control for resolving technical obstacles. I will discuss today’s selective material removal technology topics regarding low electron temperature plasma process in 3D/4F2 memory and gate all around logic

■ Challenges and reflection point for incoming memory and logic device

– Memory roadmap with 4F2/3D DRAM and >300 layer NAND

− Logic memory with Complementary FET and 2D TMD transistor

■ Selective material Removal (SMR) introduction and related application

– Recent low electron temperature plasma technology

– SMR applications for memory and logic device

■ Feasible SMR Performance and Results