Ion and Radical control technologies for the next generation seminconductor fabrication

The plasma etching technology has evolved with enhacing the controbility of Ion and radical in plasma, which can be explained sequentially by electrical separation, time separation, reaction zone separation and finally space separation. Recently we have focused on the development of the reaction zone separation with ultra-high voltage, ultra-low pressure, ultra-low temperature and ultra-high freqency plasma sources. These plasma sources can provide the strong side-passivation to prevent bowing and random distortion and the rich ion transferring to the pattern bottom to avoid not-open, which two are the most critical patterning limitations to fabricate the small pitch patterns of next generation chips. The ultra-low pressure plasma, ECR(Electro Cyclotron Resonace) can provide very stable plasma discharge even under 1mTorr which enhances the volatility of reaction gases on the surface to make the ER(Etch Rate) higher. The ECR plays the important role of small space and high A/R(Aspect Ratio) patterning for multi-Vth(threshold Voltage) tansistor fabrication at GAA(Gate All Around) device. The ultra-low temperature WF can provide very high ER and strong side-passivation even with very low polymerizing gas chemistry and this can provide very stable mass-production with clean chamber wall. We have researched very innovative etching technology of the space separation, the directional etching with tilted IBE(Ion Beam Etching) which can elongate the original patten in one direction with low incident angle beam. Especially if we can change T2T distance(Tip to Tip distance, minimum distance between neighboring patterns) we can overcom the fundamental limitation of photo lithography for the next fine pitch patterning. We already qualified the possibility of reducing easily the number of EUV layers for a device fabrication. In addition it can diminish the LER(Line Edge Roughness) efficiently with high incident angle beam to reduce the total variation of patterns in a chip, which will be the most critical problem at the future chip fabrication by inceasing the variation of transistor performance and chip yield. Those etchers at the extreme process zones and the tilted IBE will be the main stream in the future and it is very necessary to focus on them at various R&D areas.