Towards digital twins for semiconductor chip fabrication

Low temperature plasma reactors used for manufacturing these chips involve complex physical processes that are affected by a myriad of reactor operation parameters (e.g., gas pressure, temperature, applied RF voltage and frequency, the type of etchant, material, and their reaction rates). Due to the harsh and constrained environment near the wafer, comprehensive experimental diagnostics are often infeasible. As a result, predictive modeling and simulation become essential tools for understanding and optimizing these processes. In this talk, we present our work on developing a computationally efficient virtual fabrication tool that will enable process engineers to investigate the effect of the process parameters on etch uniformity. We will present our methodology to couple an external circuit with PIC/MCC simulations to predict DC bias, ion energy distribution functions, and flux uniformity. We also demonstrate how this simulation framework is integrated into a Bayesian optimization workflow, allowing for systematic identification of process parameter configurations that maximize etch uniformity.