CHIPS-TB: Evaluation of Tight-binding Models for Structural and Electronic Applications

As semiconductor technologies drive further into the nanoscale, accurate and computationally efficient methods for predicting material properties are critical. We present CHIPS-TB (Computational High-Performance Interface for Tight-binding Simulations), a new platform developed to evaluate and refine tight-binding (TB) models for structural and electronic applications in semiconductors. CHIPS-TB facilitates systematic benchmarking of TB parameters, assessing their accuracy across various structural configurations and electronic band structures, enabling robust property predictions. Special attention is given to transferability across distinct materials classes, including semiconductors, 2D materials and complex oxides, where TB models traditionally face limitations. This talk will cover the development, key functionalities, and application case studies of CHIPS-TB, with implications for integrating TB models in advanced simulation workflows. The results of this work will be made available on the JARVIS-Leaderboard (https://pages.nist.gov/jarvis_leaderboard/) benchmarking platform.