Low-noise and Low-disorder Si Quantum Dot Spin Qubits by Optimized Gate Stack Engineering

Spin qubits systems are highly sensitive to defects. While dynamic ones, also known as two-level fluctuators, impact the fidelity of quantum gates, static defects primarily limit the scalability of the system by creating non-tunable quantum dots at undesired locations. The IMEC 300mm process line leverages state-of-the-art industrial tools while maintaining high processes flexibility, making it a unique platform to address this defectivity challenge. Consequently, our efforts have focused on optimizing processes and designs to achieve very low noise [1] and low disorder quantum dots [2] in both MOS and Si/SiGe devices.



In this presentation, we will first outline IMEC’s strategy and process flows for device optimization. Given the discrepancy between the large number of devices produced by the industrial line and the time required for in-depth spin qubits characterization, validation measurements are done both in house and through extensive worldwide collaborations. We will give an overview of the results obtained on our devices across various institutions. Finally, recognizing that having a good qubit is not sufficient, we will show as an outlook an architecture relying on full back end of line processes. With this architecture, enabled by advanced optical lithography, we will now investigate scaling challenges at qubit level.