Fault tolerance in Majorana based hardware

Majorana based hardware has gained prominence as a promising platform to encode qubits and protect them against noise. In order to run computations on such devices, a fully fault tolerant scheme is needed for preparation and measurement, as well as to perform gates during the computation. In this work, we explore the possible schemes to do operations fault tolerantly on logical qubits encoded into Majorana hardware. We explore transversal gates and highlight important departures from qubit based codes, and the structure of the transversal gate group for odd vs even Majorana codes. Finally, we use the framework of reference frames to perform Clifford operations that may be forbidden under superselection symmetries. We are hopeful that this work will be useful in fermionic hardware with a set of native fermionic gates and noise model.