One Gate Scheme to Rule Them All

The design and architecture of a quantum instruction set are paramount to the performance of a quantum computer. In this talk, we introduce a gate scheme for generic quantum hardware that directly and efficiently realizes any two-qubit gate up to single-qubit gates. First, this scheme enables high-fidelity execution of quantum operations and achieves minimum possible gate times. Second, since the scheme spans the entire SU(4) group of two-qubit gates, we can use it to attain the optimal two-qubit gate count for algorithm implementation. These two advantages in synergy give rise to a quantum Complex yet Reduced Instruction Set Computer (CRISC). Though the gate scheme is compact, it supports a comprehensive array of quantum operations. This may seem paradoxical but is realizable due to the fundamental differences between quantum and classical computer architectures. Using our gate scheme, we observe marked improvements across various applications, including generic n-qubit gate synthesis, quantum volume, and qubit routing. Furthermore, the proposed scheme also realizes a gate locally equivalent to the commonly used CNOT gate with a gate time of π 2g , where g is the two-qubit coupling. The AshN scheme is also completely impervious to ZZ error, the main coherent error in transversely coupled systems, as the control parameters implementing the gates can be easily adjusted to take the ZZ term into account.