Scaling-up quantum processors with chiplet-based architectures and inter-modular tunable couplers

Nowadays superconducting quantum processors with hundreds of qubits are being produced and operated by few institutions and companies. However, these large monolithic devices present significant engineering and physics challenges. Key issues include suppressing flux and microwave crosstalk, achieving precise frequency targeting to optimize performance and avoiding frequency collisions, or substantially reducing the rate of Josephson junction failure. Even minor failures in these critical elements can result in poorly or entirely unusable devices. As we push towards building even larger systems aimed at quantum utility applications and fault-tolerant machines using error-correcting codes, these challenges will become increasingly severe and difficult to address.

We propose approaching the scalability challenge with a chiplet-based architecture. This involves interconnecting high-performance, small-scale quantum devices via a modular intra-chip tunable coupler to enable interactions between qubits across separate chips without degrading performance. In this talk, I will review experimental data on key components for building large-scale devices using chiplet architectures. Starting with operational procedure and performance measurements of our 9-qubit chiplet device, to conclude demonstrating the effectiveness of our inter-modular approach.