Scalable, hardware-efficient quantum error correction using concatenated cat qubits
ORAL · Invited
Abstract
In this talk I will present recent work [1-3] out of the AWS Center for Quantum Computing to develop error-corrected logical qubits on a superconducting quantum circuit hardware platform using simplified outer codes composed of dissipatively stabilized cat qubits. I will present important details underpinning the effectiveness of this approach, and discuss future opportunities and challenges in device scaling and logical error rate reduction.
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Publication: [1] "Hardware-efficient quantum error correction using concatenated bosonic quibuts," arXiv:2409.13025<br>[2] "Preserving phase coherence and linearity in cat qubits with exponential bit-flip suppression," arXiv:2409.17556<br>[3] "Hybrid cat-transmon architecture for scalable, hardware-efficient quantum error correction," arXiv:2410.23363
Presenters
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Oskar Painter
Caltech, Caltech & AWS, AWS Center for Quantum Computing
Authors
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Oskar Painter
Caltech, Caltech & AWS, AWS Center for Quantum Computing