A biased-erasure architecture in 3D superconducting cavity

Quantum error correction (QEC) is crucial for mitigating the impact of decoherence on qubits and enabling fault-tolerant quantum computation. However, traditional QEC schemes that rely on qubits subject to Pauli errors often come with significant hardware overhead. Recently, erasure qubits have emerged as a promising alternative, offering improved scalability and higher thresholds by performing error detection at the single-qubit level. Interestingly, biased-erasure qubits–a variant of standard erasure qubits–are predicted to further enhance these thresholds. Unlike standard erasures, which affect both computational states of the qubit, biased-erasures cause detectable leakage from only one of the computational states. In this talk, we introduce a novel biased-erasure qubit which encodes the quantum information in the 0 and 2 Fock states of a single harmonic oscillator. We realize this logical qubit in a 3D superconducting microwave cavity coupled to an ancilla transmon which enables logical Z-basis readout and fault-tolerant single-qubit gates in the 0-2 code space. We convert photon loss in the cavity into a biased-erasure by detecting decay of the 2 Fock state into the 1 Fock state. Additionally, we incorporate a reset in our mid-circuit erasure checks, which autonomously restores the system back to the logical codespace. These erasure checks introduce minimal back-action on the system while the reset operation eliminates the need for postselection. Finally, we demonstrate the implementation of a two-qubit gate between two biased-erasure qubits to prepare a logical Bell state. This work provides a comprehensive set of tools for implementing an erasure qubit in a single physical system, offering promising reductions in hardware overhead for scalable QEC.