Modeling Logical Errors for Surface Code Circuits through Trapped-Ion Hardware Emulation

With fault-tolerant quantum computing (FTQC) on the horizon, it is critical to understand sources of logical error for plausible hardware implementations of quantum error-correcting codes (QECC). Detailed error modeling for computational instructions on particular FTQC architectures will enable better prediction of error propagation in FT-encoded quantum circuits, while revealing where greater attention is needed in hardware design. In this work, we model logical errors for circuits that perform logical transformations on surface codes implemented on a grid-based trapped-ion quantum charge-coupled device (QCCD) architecture. To this end, we construct channel representations for surface code logic circuits and examine their fault-tolerance under realistic noise assumptions. To emulate noisy, non-Clifford hardware circuits at practical code distances in a manner that is asymptotically exact, we utilize a Monte Carlo technique to sample from an underlying quasi-probability distribution of Clifford circuits.