Scalable Universal Digital Functionality in Low-Power Skyrmion Logic Circuits

Magnetic skyrmions have emerged as highly efficient, ultra-low-power information carriers, thanks to their nonvolatile nature and fast processing capabilities. However, the development of skyrmion-based logic systems that can scale effectively has been challenged by several issues, such as non-universality, inefficient charge-to-spin conversion, energy consumption, thermal drift, synchronization, and scalability constraints. Here, we show a scalable skyrmion logic circuit scheme, focusing on the design, simulation, and emulation of a universal, scalable system utilizing a tiled skyrmion block matrix. Using micromagnetic simulations, we address the challenges mentioned and create a scalable skyrmionic logic system.



Building on our previously developed skyrmion inverter [1] and introducing newly designed blocks and an emulation system, we constructed a variety of logic gates—including NOR, AND, OR, NAND, and FULL ADDER—by cascading and configuring skyrmion blocks[2]. We optimized the circuit performance using micromagnetics and our emulation software. Our modular design helps create complex, customizable logic circuits with low energy consumption.



Translating this theoretical work into practical applications presents challenges such as Joule heating, geometric pinning, polycrystallinity, and the Skyrmion Hall Effect (SkHE). Joule heating can potentially be reduced by using 2D materials, magnetic insulators, or skyrmion-hosting semiconductors instead of ferromagnetic layers. Geometric pinning can be minimized through improved fabrication and reduced polycrystallinity. SkHE can be minimized using Synthetic Antiferromagnets (SAF) instead of ferromagnetic layers[3,4]. Overall, we demonstrate a universal, scalable, and Boolean-universal skyrmion-based logic circuit that uses skyrmions exclusively as signal carriers, paving the way for ultra-low-energy computation. This work represents a key progress towards integrating skyrmionics into hardware description languages.