Oral: A Scalable Cryogenic Quantum Control and Readout Plane with Integrated ARM Processor for Silicon Qubits

Quantum computers are transitioning from the NISQ (Noisy Intermediate Scale Quantum) to the FTQC (Fault Tolerant Quantum Computing) Era. That transition is facilitated by massive scaling, not only in the Quantum Processor, but also in the control and readout plane. In addition, the requirements for real time error correction stipulates a low latency interface between the classical and quantum processor. In this work, we present a monolithic integration of spin qubits in Si with cryogenic electronics and a localized ARM processor fabricated in the 22FDX fully depleted silicon-on-insulator (FD-SOI) technology from GlobalFoundries. The circuits perform various functions that include DC biasing, voltage pulsing, ESR control and direct current measurement of charge sensors that are integrated with an array of qubits. The DC biasing and pulsing is achieved with 10-bit capacitive DACs driven by digitally controlled high speed pulse generators. The on-chip cryogenic memory stores unique patterns to generate various quantum gate behaviors. The readout circuit comprises a CTIA, a CDS and a 1-bit ADC with an integration time of 500ns while consuming 200µW of power. The quantum control and readout tile houses 64 voltage pulsers and 8 detectors occupying an area of 0.28mm² with a power budget of < 1mW per qubit for control and readout at 3.5K. Therefore, the highly scalable architecture with localized AI enhanced Quantum Error Correction loop paves the way for achieving fault tolerant quantum operation.