FASQuiC : An Heterogeneous Distributed Architecture for Scalable Qubit Feedback Experiments

Significant efforts within the quantum computing community are focused on developing scalable, flexible, and low-latency FPGA architectures for quantum control. The majority of the state-of-the-art architectures are AWG-based [1]–[13], largely due to the requirements of superconducting qubits. However, this AWG-based approach has severe limitations in terms of scalability and feedback latency. Furthermore, none of these architectures meet the specific needs of other qubit technologies such as spin qubit platforms.



In this presentation, we outline our FPGA solution : FASQuiC (Flexible Architecture for Scalable Spin Qubit Control). FASQuiC is scalable in terms of resources and feedback latency due to its heterogeneous, distributed architecture, which includes dedicated lightweight processors. It also embeds Direct Digital Synthesis (DDS) signal generators for ramps and sine combs [14] tailored for scalable spin qubit control. Up to now, two hardware accelerators have been developed in the heterogeneous architecture for the fast initialization of qubit states, and embedded Randomized Benchmarking (RB).



FASQuiC is capable of generating programmable combinations of ramps, frequency combs, and AWG at 5 GS/s with a maximal waveform reconfiguration latency of 76.8 ns. In terms of feedback latency, fast initialization of Singlet or Triplet state has been successfully conducted on a spin qubit device with digital latency of 137.6 ns. The RB hardware accelerator generates a random gate among a Clifford set on-the-fly with less than 58.4 ns of deadtime and compute the inverted gate in 89.6 ns.