A multi-length qubit coupler architecture for large-scale, error-corrected superconducting quantum computers

With recent advances in low-density parity check (LPDC) error correcting codes, the hardware overhead for implementing error-corrected superconducting quantum processors units (QPUs) has been reduced by approximately one order of magnitude for most relevant resource constraints as compared to a surface code implementation. To build a large-scale computational system that can grow from 200 to 2000 logical qubits over the timeline of 2029 to 2033, we must interconnect many physical QPU payloads. A heterogeneous coupler architecture will therefore be required to provide two qubit gates and/or entanglement generation between superconducting qubits over length scales from approximately 1 mm to 1 m. In this talk, I will present IBM's roadmap to build such a system, share current progress on key enabling technologies, and highlight key challenges for the academic and industrial ecosystem.