Addressable Superconductor Integrated Circuit Memory from Delay Lines

Recent advances in logic schemes and fabrication processes have renewed interest in using superconductor electronics for energy-efficient computing and quantum control processors. However, the development of scalable superconducting memory remains a critical challenge. We address this limitation by introducing a delay-line memory system that diverges from conventional efforts focused on memory cell miniaturization. Our architecture integrates a high-speed Josephson junction-based controller for read/write operations with low-velocity factor superconducting loops, constructed from high kinetic inductance materials or long Josephson junctions, for storing data in the form of single flux quanta. This approach minimizes energy consumption while maximizing data density, with estimates suggesting capacities of 10 to 100 Mbit/cm². Initial fabrication results verify the functionality of the proposed controller and validate the storage density models for MoN high-kinetic inductance delay lines. Variability analyses, which account for timing jitter and dispersion, indicate error-free operation in loop sizes of 30-50 bits at 50 GHz speeds and provide helpful insights into optimizations for the microarchitecture and data organization.