Controlling dissipation of bit erasure in stochastic logic circuits

Landauer's principle and developments from stochastic thermodynamics provide insight into the energetic costs of logical operations. As transistors on chips become smaller, one must begin to consider the effects of thermal fluctuations that approach the magnitude of the correspondingly smaller operating voltages. We use a thermodynamically consistent model of a 1-bit static random access memory (SRAM) device constructed from NOT gates to explore dissipative costs of bit erasure. By deriving a low dimensional representation of the system, we leverage prior studies on optimal control to deduce low dissipation erasure protocols. With knowledge of optimal protocols in this simplified picture, we consider how to apply the same principles to more complex noisy, nanoscale circuits.