Characterization of industrially-fabricated two-dimensional quantum dot arrays

Quantum-error-correction codes impose significant requirements on the number of physical qubits required in quantum processors. This number generally decreases as the degree of qubit connectivity in a given topology is increased. Spin qubits based in silicon quantum dots are well-positioned to be scaled to large numbers as they are inherently small in size and can leverage decades of semiconductor fabrication infrastructure and investment. However, silicon-based spin qubits have largely been limited to one-dimensional chains of quantum dots which restricts the degree of qubit connectivity achievable. More recently, two-dimensional arrays of quantum dots, which are necessary to improve both the number of qubits as well as the qubit connectivity, have been demonstrated in silicon- and germanium-based heterostructures. Here we present results from 3x3 arrays of quantum dots fabricated entirely on Intel's 300mm fabrication line. A key feature of these devices is the use of multiple metal layers and vias to route the gate electrodes, which enables the high gate-density required for two-dimensional arrays and, importantly, is extendable to even larger arrays of dots. We demonstrate that we can tune the entire array to the single-electron regime, and present progress towards encoding qubits in these devices.