Simulation-based optimization of industrially-compatible FD-SOI spin qubit devices

Silicon spin qubits are among the most promising technologies for scalable quantum computing. Leveraging industrial fabrication processes allows for reduced variability. FD-SOI (Fully Depleted Silicon on Insulator) has already proven to be a viable platform for silicon spin qubits [1].

However, the dimensions achievable using commercially available FD-SOI technology are less aggressive than those from non-industrial techniques. In this work, simulations illustrate the advantages of employing smallest pitch allowed by 193nm immersion lithography over the pitch used in the commercial FD-SOI technology. The investigated structures are linear and bilinear arrays with one side hosting the qubits and the other side hosting the sensors. Simulations reveal improved maximum tunnel coupling between neighboring qubits, and optimized geometries deliver sufficient capacitive coupling between qubits and sensors. Finally, we explored the impact of device dimensions into qubit-to-qubit variability by simulating the impact of single charge traps on qubit properties.

[1] Maurand, R., et al (2016)