Thermal modelling of cryogenic input-output platforms for scaling superconducting quantum computers beyond 1000 qubits

A key bottleneck in scaling superconducting quantum computers to the degree required for practical computation is the Input-Output (IO) connectivity between the quantum processor, housed in a milli-Kelvin environment, and control elements. Scaling the quantum processor to millions of physical qubits and enabling fault tolerance quantum compute enforces stringent requirements on the interconnection density, signal integrity and latency. This results in equally stringent requirements on the cryogenic system to support the distributed heat loads associated with the control electronics and interconnections.

This work presents a novel thermal model as a design tool for scaling cryogenic IO platforms for quantum computing, with applicability to other cryogenic technologies. We construct a comprehensive capacity map of a dilution refrigerator, used to predict the impact of an arbitrary IO ‘payload’. Rather than treating temperature stages as isolated with fixed cooling power, we account for interdependencies resulting in dynamic effects between stages to accurately model the payloads inclusion. The model's predictions are compared with experimental results and used to make inferences about performance overheads and payload design for a platform scaled beyond 1000 qubits.