A novel architecture for silicon quantum dot spin qubits

Spin qubits in semiconducting quantum dots possess advantages for scaling due to their small size and compatibility with the 300mm-wafer processing. However, the demonstration of multi-qubit systems in silicon has so far been reported only for single linear qubit arrays. With the recent demonstration of high-fidelity qubit shuttling in a silicon linear array, more complex qubit architectures can be considered to further scale the number of qubits while achieving high connectivity. Here, we propose a novel architecture for Si quantum dot spin qubits that leverages shuttling while allowing for efficient single and multi-qubit control and read-out. We present the design of such an architecture and discuss its advantages and limits for the qubit operation and integration, including the development of multilayer interconnect routing. Given the connectivity, we expect the architecture to also enable more advanced error correction schemes that require beyond-nearest neighbor connections.