Fault-Tolerant Quantum Computing with Emulated Anyons on Superconducting Qubits
ORAL
Abstract
Achieving fault-tolerance through brute-force error correction schemes is expected to require a superconducting quantum processor with millions of physical qubits. In this scheme, superconducting circuit elements (e.g. transmon or fluxonium) form physical qubits at the hardware level. An error correction scheme, such as the surface code, is then employed at the software layer to form a logical qubit.
While significant progress has been made, and recent experiments have successfully demonstrated the feasibility of such method, the hardware overhead seems prohibitive for a commercially relevant machine. In this talk, we will introduce an alternative pathway to achieve fault-tolerance with superconducting qubits that has the potential to significantly reduce the error-correction overhead.
In this approach, we arrange physical superconducting circuits such as transmons (which we will referred to as Layer-0 qubits) in lattices. Each Layer-0 qubit is coupled to its neighbors through a set of tunable couplers that allow the neighboring qubits to enter deep-strong coupling regime. We will discuss example designs and physics of such couplers. Each lattice will form a man-body system with two degenerate ground states protected by a significant energy gap. We will show that these ground states defer in parity. Quantum information encoded in these degenerate states will have exponential protection against an error channel (e.g. bit-flip error). We call this encoding a Layer-1 qubit.
We demonstrate that a Layer-1 qubit is akin to a topological qubit and one can construct a set of gates by emulating braiding of non-abelian Anyons. We will provide examples of single and two qubit gates in such scheme and provide estimates of expected gate fidelities. We will also provide estimates on the hardware and software overhead to perform error-correction schemes to form a logical qubit, which will be referred to as Layer-2 qubits, from a set of Layer-1 qubits.
While significant progress has been made, and recent experiments have successfully demonstrated the feasibility of such method, the hardware overhead seems prohibitive for a commercially relevant machine. In this talk, we will introduce an alternative pathway to achieve fault-tolerance with superconducting qubits that has the potential to significantly reduce the error-correction overhead.
In this approach, we arrange physical superconducting circuits such as transmons (which we will referred to as Layer-0 qubits) in lattices. Each Layer-0 qubit is coupled to its neighbors through a set of tunable couplers that allow the neighboring qubits to enter deep-strong coupling regime. We will discuss example designs and physics of such couplers. Each lattice will form a man-body system with two degenerate ground states protected by a significant energy gap. We will show that these ground states defer in parity. Quantum information encoded in these degenerate states will have exponential protection against an error channel (e.g. bit-flip error). We call this encoding a Layer-1 qubit.
We demonstrate that a Layer-1 qubit is akin to a topological qubit and one can construct a set of gates by emulating braiding of non-abelian Anyons. We will provide examples of single and two qubit gates in such scheme and provide estimates of expected gate fidelities. We will also provide estimates on the hardware and software overhead to perform error-correction schemes to form a logical qubit, which will be referred to as Layer-2 qubits, from a set of Layer-1 qubits.
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Presenters
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Alireza Najafi-Yazdi
Anyon Systems Inc
Authors
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Alireza Najafi-Yazdi
Anyon Systems Inc