Characterization and compilation of hardware efficient gates

Entangling gate families parametrized by continuous parameters have recently gathered significant interest since they are typically shorter, using up a smaller fraction of the qubit coherence time available. Fast and efficient calibration of such shorter, high fidelity entangling gates and the construction of optimal circuit synthesis schemes that leverage the richer gate set are open problems that we address in this work.

We develop a novel gate calibration technique that is highly resource efficient in terms of both QPU time and classical post-processing time. It relies on building a faithful model for the gate Hamiltonian that includes the contribution of coherent error terms. Our specialized compiler features a unitary synthesis algorithm that is able to use such model definitions to construct circuits which have shorter depths and higher fidelity.

We demonstrate the power of this fully automated technique experimentally on cross resonance gates on IBM Quantum devices by adding to the existing entangling gate set, shorter duration efficient gates by utilizing only 3 min of QPU time and 30s of classical post-processing time. Our algorithmic benchmarking of these techniques allows us to get up to 3 times higher success probability in the QFT algorithm for up to 24 qubits.