Co-Designing the QPU's topology for a quantum algorithm

While the efforts for fault-tolerant Quantum Processing Units (QPUs) advance, several strategies are developed to pursue early quantum advantage making use of Noisy Intermediate-Scale Quantum devices. One of these strategies is the Co-Design of quantum hardware and algorithms, through the design and fabrication of Quantum Application Specific Integrated Chips (QuASICs). [1]



Transpiling a quantum algorithm to a QPU with limited connectivity introduces the need of SWAP gates and a deeper circuit, producing more errors in the computation. In this talk, we discuss recent progress on Co-Designing a QPU’s topology (its physical two-qubit connections) to a specific algorithm’s structure (its two-qubit gates), showing how this can reduce the number of required SWAP gates, as well as the extra depth introduced by them. We further quantify the effects of choosing a particular QPU topology on generic quantum algorithm performance, and show how to adapt this quantitative study to design and analyze QuASICs. To illustrate this, we discuss the design of a QuASIC for a specific quantum algorithm, and analyze its performance compared to two-dimensional lattice QPUs, such as the square lattice.



[1] M.G. Algaba et al., “Co-Design quantum simulation of nanoscale NMR” (2022), arXiv:2202.05792

[2] B. Lu et al., “Special-Purpose Quantum Processor Design” (2021), arXiv:2102.01228