Interplay of embedding and chip connectivity in quantum annealing

The feasibility of combinatorial optimization problems to be solved on quantum annealers strongly depends on the ability to represent their problem graph on the physical chip architecture. Especially the connectivity between qubits proves to be of crucial importance in addition to the number of qubits itself. This is due to the reduced need of long, error-prone qubit chain encoding when the connectivity can be mapped directly. However, more than needed physical connectivity can introduce additional noise and thereby logical errors. We examine the tradeoff between those opposing effects and deduce a model of suitability of chip architectures for certain kinds of problems graphs. For evaluation, we focus on the success probability of respective solving attempts.