Integrating Si/SiGe quantum devices with on-chip classical circuitry

The rapid acceleration of quantum computing technologies is poised to reach an interconnect bottleneck, where the qubit count in a quantum processor is limited by the number of input-output (I/O) connections. We demonstrate the operation of an on-chip classical multiplexer on an array of Si/SiGe quantum Hall devices that reduces the I/O connections on the chip by nearly ten fold, with a Rent exponent p = 0. We use the Hall devices to characterize the performance of the integrated switches at 2K and high magnetic fields. We measure the signal bandwidth through the multiplexing circuit and discuss a protocol for multiplexed charge-sensing readout of quantum-dot qubits equipped with this technology. We discuss the impact of the finite bandwidth on single-shot readout fidelity for an array of N quantum dot charge sensors.