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A 200 mm Wafer Size Superconducting Qubit Foundry at MIT Lincoln Laboratory

ORAL

Abstract

MIT Lincoln Laboratory has worked over the course of more than a decade to establish robust, reliable superconducting qubit fabrication processes. Recently, we have piloted a superconducting foundry model to provide access of its robust, high-yielding process to the US quantum research and development community. Initially established on 50 mm silicon wafers, we have ported our core process to the Laboratory's 90 nm capable, Class-10, 200 mm wafer size Microelectronics Laboratory (ML). This Trusted, ISO9001 facility contains automated cluster tools with improved process resolution and control, automated defect inspection and characterization for improved yield, in-line metrology, and additional real estate to accommodate multiuser runs. We will discuss the development of this 200 mm process, in particular the development of a superconducting air bridge process and of a flip-chip process for 2-D chip stacking.

Presenters

  • Jeffrey Knecht

    MIT Lincoln Lab, MIT Lincoln Laboratory

Authors

  • Jeffrey Knecht

    MIT Lincoln Lab, MIT Lincoln Laboratory

  • Cyrus F Hirjibehedin

    MIT Lincoln Lab

  • Kate Azar

    MIT Lincoln Laboratory

  • Bethany M Niedzielski

    MIT Lincoln Lab, MIT Lincoln Laboratory

  • Michael A Gingras

    MIT Lincoln Lab, MIT Lincoln Laboratory

  • David K Kim

    MIT Lincoln Lab, MIT Lincoln Laboratory

  • Alexander Melville

    MIT Lincoln Laboratory

  • William D Oliver

    Massachusetts Institute of Technology MIT, Massachusetts Institute of Technology (MIT), MIT Lincoln Laboratory, Massachusetts Institute of Technology (MIT), Massachusetts Institute of Technology, Massachusetts Institute of Technology, MIT Lincoln Laboratory

  • Meghan Schuldt

    MIT Lincoln Laboratory, MIT Lincoln Lab

  • Mollie E Schwartz

    MIT Lincoln Laboratory

  • Jonilyn L Yoder

    MIT Lincoln Lab, MIT Lincoln Laboratory