Automation of quantum-chip selection using supervised machine learning.

Designing a scalable superconducting quantum processor is a challenging task that requires a complex frequency allocation procedure as well as elaborate simulations to mitigate crosstalk effects. However, achieving an acceptable fabrication yield for such complex structures is even more difficult. The yield analysis at the wafer level results in variations across the wafer on the order of a few percent, which is mainly attributed to variations in the junction area and tunneling thickness. However, imperfections at the chip level can limit the yield even if a single qubit fails. We developed a tool based on room-temperature junction resistance measurements to automate the classification of failure modes at the wafer and chip level, to speed up fabrication development, and to automate chip sorting. This tool relies on supervised machine learning algorithms, which facilitate fabrication-statistics extraction and the clustering of good and bad chips in a systematic way.