Error correcting codes on near-term devices of quasi-linear and central-spin-like connectivity

We evaluate the performance of small error-correcting codes which we implement on hardware platforms of very different connectivity and coherence: On a superconducting processor and on a spintronic quantum register consisting of a colour centre in diamond. Taking the hardware-specific errors and connectivity into account, we investigate the dependence of the resulting logical error rate on the platform features such as the native gates, the native connectivity, gate times and coherence times. We investigate different recovery schemes for the encoded quantum state based upon the classical information obtained by the measurement outcome. Using an error model parametrized for the given hardware, we simulate the performance and benchmark these predictions with experimental results when running the code on the superconducting processor. The results indicate that for small, low-weight parity check codes, the hexagonal, quasi-linear layout proves advantageous, yet for codes relying on controlled multi-qubit operations with high-weight stabilizers, the CSS-like connectivity and native Toffoli gate of the colour centre enables a favourable transpilation.