Design and optimization of a cryogenic CMOS capacitance bridge for readout of silicon spin qubits

Despite recent success in the field of quantum information, a clear path to a scalable quantum computing architecture has yet to be found. As the number of high-fidelity qubits in a device increases, so too does the amount of control electrodes and readout structures, rapidly leading to significant connectivity issues.

One promising approach to mitigate this problem is to leverage the considerable experience of the semiconductor manufacturing industry to co-integrate control electronics with quantum dot qubits hosted in silicon. This allows for long-demonstrated classical circuits to exist on the same chip with quantum structures to significantly improve throughput and readout sensitivity while reducing the amount of necessary control lines.

Here we present results demonstrating the operation of a CMOS capacitance bridge suitable for readout of silicon spin qubits. We show sensitivity approaching the attofarad regime for a simplified circuit below 4 K using two different technology nodes - 28nm Fully Depleted Silicon On Insulator (FD-SOI) from STMicroelectronics and TSMC 180nm via CMC Microsystems. We also present simulations for an optimized bridge with attofarad sensitivity capable of operating over a large range of frequencies.