Etching SiO2 on Si wafers to develop an array of tip well-trench structures for potential freestanding graphene energy harvesting.

Freestanding graphene is so flexible it moves under the slightest influence. In this study, we use is a silicon wafer to create a stable platform on which to potentially capture this kinetic energy. A 1 cm by 1 cm chip is cut from a silicon wafer having a 2-micron thick thermal oxide on top. We spin coat the chip with polymethyl methacrylate and bake. Next we use electron beam lithography to pattern the surface. The pattern is an array of well-trench structures. However, the well pattern contains a "hat" at its center to block surface etching. The chip is then submerged in a buffered oxide etchant (BOE) for 5 to 10 minutes. The BOE undercuts the "hat" to naturally form a cone shaped tip in the SiO2 at the center of the well due to isotropic etching. We characterize the etched surface using optical and atomic force microscopy. The goal is to have the trench depth around 1 micron. The well is square shaped with a width around 7 microns. The top of the SiO2 tip is 0.5 microns below the top surface of the wafer, which is where the graphene is ultimately suspended from.