Building Superconducting Quantum Hardware towards Error-Corrected Quantum Computing

Quantum Computers will ultimately rely on near-perfect logical gates, implemented while correcting errors at the physical level. The need for developing quantum hardware optimized for performing fast, repeatable, and high-fidelity syndrome measurements in quantum error-correcting codes such as the surface code therefore becomes increasingly important. In my talk, I will present advances in performing qubit readout and two-qubit gates in multi-qubit superconducting quantum processors, which enabled the recent experimental demonstration of repeated quantum error correction in surfaces codes. I will show how quantum processors optimized for quantum error correction can also serve as a testbed to explore noisy intermediate-scale quantum algorithms. The talk will conclude with a discussion about open challenges and opportunities to advance the speed and fidelity of syndrome detection in scalable device architectures by exploiting tunable coupling elements.