Modeling Current Flow through Copper with Rough Surfaces

Interconnects are a key component of integrated circuits (IC) and play a major role in the speed and power consumption of an IC. While surface roughness is essential for ensuring adhesion to other components in an IC, it also increases electron scattering at the surface which can dramatically increase resistivity. Using a combination of density functional theory (DFT) and the non-equilibrium Green’s function technique in conjunction with DFT (NEGF-DFT), our work aims to identify key tradeoffs between surface roughness profiles and electronic performance in copper wire interconnects. Our work suggests a connection between the local potential and increases in resistance for atomic-level defects and raises the possibility that a roughness profile could be engineered so as to minimize negative effects on electronic performance. We extend this investigation to nanometer-level surface roughness profiles, and also investigate other compositions commonly used in industry, such as Cu₃Sn. This work has the potential to help realize low-resistivity interconnects, reducing power consumption and increasing speed in integrated circuits.