Distributed Union-Find Decoder and Its FPGA-based Implementation for Scalable Quantum Error Correction

A fault-tolerant quantum computer must decode and correct errors faster than they appear. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than O(d³), substantially better than the more accurate MWPM decoders. We report a distributed version of the UF decoder that exploits parallel computing resources to further speed up. Given O(d³) parallel computing resources, the distributed UF decoder has an average time complexity of O(log(d)), without considering communication cost between the parallel resources. We design Helios, a scalable architecture that organizes parallel computing resources into a hybrid tree-grid structure and report an FPGA-based implementation of Helios and the distributed UF decoder. Using Xilinx’s cycle-accurate simulator, we show that the average decoding time of our implementation grows sublinearly with regard to d, up 15, with phenomenological noise model p=0.1%. We also confirm the decoding time with a Xilinx ZC106 FPGA for d up to 7: the FPGA does not have enough resources to support d>7 but achieves an average decoding time of 830 ns for d=7. We will also report our ongoing implementation effort using a network of seven Xilinx FPGAs, with a goal to support d=13.