Improving algorithmic performance of tunable superconducting qubits using deterministic error mitigation

The largest NISQ era devices currently available utilise superconducting architectures. Flux tunable superconducting qubits in particular help avoid frequency collisions in large devices, and can utilize fast gates and measurement schemes. However, such architectures are affected by higher sensitivity to flux noise that affects gate fidelities, in addition to decoherence and readout errors that inhibit the performance of all NISQ era devices, leading to sub-optimal accuracy on even few qubit algorithms. In this work, we show how our deterministic error mitigation pipeline improves the performance of superconducting hardware on algorithmic benchmarks. In particular, we utilize intelligent quantum compilation and physics-aware circuit layout selection strategies, optimized single and two qubit gate calibration, measurement readout error mitigation, and correlated dynamical decoupling, to reduce errors at every stage of the quantum hardware stack. We demonstrate these methods on a Rigetti quantum computer, and show over a 1000 X and 30 X improvement in accuracy on 15 qubit Bernstein Vazirani and 7 qubit Quantum Fourier Transform circuits respectively. We also show that our calibration methods efficiently improve single and two qubit gate fidelities across the device, leading to improvements of more than 7 X over default fidelities. We also show that our methods suppress idling errors and crosstalk across the device, leading to a significant increase in quantum volume of the quantum computer.