Interaction graph-based profiling of quantum circuits for algorithm-aware mapping techniques

Quantum circuit mapping techniques are crucial for successfully executing quantum algorithms on current resource-constrained and error-prone quantum processors. They perform some modifications on the quantum circuit so that it complies with the hardware restrictions, while trying to minimize the resulting gate and depth overhead to increase the circuit success rate. Most quantum circuit mapping techniques focus on the hardware properties, though some works have already pointed out the importance of also considering algorithm characteristics.

We perform thorough profiling of quantum circuits by not only extracting parameters like the number of qubits and gates and two-qubit gate percentage, but also graph theory-based metrics from their corresponding qubit interaction graph (distribution of two-qubit gates among qubits) and gate-dependency graph (relations between gates). In-depth profiling of quantum circuits could be significant to: i) have a deeper understanding of why some circuits have higher fidelity than others when being run on a particular processor using a specific mapping technique and ii) develop application-driven mapping methods.

After clustering the quantum circuits based on the derived parameters and graph metrics, we observe a clear correlation between them and the mapping and circuit performance metrics (i.e gate and latency overhead and fidelity) when considering the constraints of three different superconducting quantum processors.