Using Quantum Hardware Speed Limits to Improve Basis Gate Selection

Increasing Quantum Circuit (QC) fidelity requires an efficient co-designed instruction set which minimizes the use of costly gate applications. The choice of a hardware basis gate depends on a QC’s native Hamiltonian interactions among the qubits. However, calibrating gates is an expensive process, so we inspect the Hamiltonian along with quantum algorithms to find which single gate type yields the shortest overall circuit duration, and therefore maximum overall circuit fidelity. We use gate durations and expected costs from Haar random unitaries to design transpilation passes using numerical decomposition tools. We characterize hardware speed limits in a case study of a SNAIL modulator to find the maximum driving strengths given a gate’s interaction parameters. Next, we optimize the interleaved 1Q and 2Q gate templates using monodromy polytopes [Peterson, et. Al, Quantum 4 (2020)] and a Hilbert-Schmidt cost function. We also extend our decomposition tool using entropic measures to perform entangled state creation. We will present our recent simulated fidelity improvements using our software tool. Finally, we will also comment on the limitations of gate optimizations because of controlled-unitaries dominating quantum algorithm designs.