Simulation of Parallel Gate Fidelities in 1D and 2D Arrays of Noisy Flip-Flop Qubits

The anti-parallel spin states of the nucleus and the bonded electron of a ³¹P atom located in a ²⁸Si substrate form a good quantum system to define a qubit, the Flip-Flop Qubit (FFQ) [1]. One-qubit operations have been experimentally demonstrated in a FFQ this year [2] and two-qubit gates are foreseen to be generated by using the electric dipole-dipole interaction between a couple of FFQs [1]. This long-range dipole-dipole interaction can be exploited to relax the common device fabrication requirements on the lateral positioning of top metal electrodes from a range of few tens nm in quantum dot-based qubit arrays to one of few hundreds nm in FFQ arrays. Parallel gating, that’s the simultaneous application of gates on many qubits, is limited by unwanted inter-qubit interactions thus narrowing the quantum error correction (QEC) codes effectiveness to achieve the long-term goal of a fault-tolerant quantum computation. Parallel one-qubit and two-qubit gate fidelities are simulated in 1D [3] and 2D arrays when embedded in a realistic noisy environment. We analyze the parallel gate fidelity results obtained in different configurations of active/idle FFQs for some inter-qubit distances, exploring strategies to mitigate the unwanted interaction effects and to enhance the performances of selected QEC codes. [1] Tosi et al., Nat. Comm. 2017, 8450. [2] Savytskyy et al., arXiv:2202.04438. [3] Rei et al., Adv. Quantum Technol. 2100133 2022.