Quantum dot arrays in linear and two-dimension geometries in silicon

The performance of quantum computers can be traced back to the quality of quantum devices. Quantum states are fragile and may lose their state due to decoherence caused by a noisy environment [1,2,3]. The growth of low defect, and low disorder materials and reliable device fabrication is required. In this work, we report on state-of-the-art fabrication methods of spin qubit devices that are defined in isotopically purified in-house grown 28Si/SiGe heterostructures. We report developments in the fabrication process of two-dimensional quantum dot arrays in 28Si/SiGe heterostructures as a promising way forward for scaling up [4]. Such a device architecture also allows for tunnel coupling between two adjacent quantum dots in two-dimensions. Furthermore, scalable quantum processor might also require the use of shared plunger and barrier gates as has been demonstrated in the Ge/SiGe material platform [5], which entails very high level of device uniformity in terms of control voltages required per qubit. Here, we also report on fabrication process of linear quantum dot array devices that were used to demonstrate the electrical tuning of plunger gates to achieve higher degree of electrical uniformity, thereby significantly reducing variations in the turn-on voltages [6].

[1] Zwanenburg et al., Rev. Mod. Phys. 85, 961 (2013).

[2] Nicollian and Brews, MOS (Metal Oxide Semiconductor) Physics and Technology, (John Wiley & Sons, New York, 1982).

[3] Wuetz et al., arXiv: arXiv:2209.07242.

[4] Vandersypen et al., npj Quantum Inf 3, 34 (2017).

[5] Borsoi et al., arXiv:2209.06609.

[6] Meyer et al. (to be submitted)