Impact ionization-induced bistability in cryogenic CMOS transistors for capacitorless memory applications

Cryogenic operation of complementary metal oxide semiconductor (CMOS) silicon transistors is crucial for quantum information science. We report bistability and dramatic hysteretic loops that are observed in the drain current as a function of gate voltage characteristics I_D(V_G) of 180 nm, foundry fabricated, CMOS transistors operated at low temperatures (T<30 K). The hysteretic loops – which have a >10⁷ ratio of high to low drain current states at the same V_G – can be used for a capacitorless single-transistor memory at cryogenic temperatures. The bistable behavior occurs when the transistors are operated at voltages exceeding 1.3 V at cryogenic temperatures and can be obtained from both n-type and p-type transistor polarities. The device bistability arises from impact ionization charging of the transistor body, which leads to effective back-gating of the inversion channel. This physical mechanism was verified by independent measurements of the body potential where voltages as large as ≈1 V are seen. The retention time at cryogenic temperatures is many minutes, sufficiently long to provide effectively nonvolatile memory on the time scales predicted for quantum computation controlled and read out by CMOS circuitry.