Hole spin qubits in silicon fin field-effect transistors

Quantum computing's greatest challenge is scaling up. Several decades ago, classical computers faced the same problem and a single solution emerged: very-large-scale integration using silicon. Today's silicon chips consist of billions of field-effect transistors (FinFETs) in which current flow along the fin-shaped channel is controlled by wrap-around gates. The semiconductor industry currently employs fins of sub-10 nm width, small enough for quantum applications: at low temperature, an electron or hole can be trapped under the gate and serve as a spin qubit. An attractive benefit of silicon's advantageous scaling properties is that quantum hardware and its classical control circuitry can be integrated in the same package. This, however, requires qubit operation at temperatures greater than 1 K where the cooling is sufficient to overcome the heat dissipation [Petit et al., Nature 580, 355 (2020); Yang et al., Nature 580, 350 (2020)].

 

In this talk it will be shown that a silicon FinFET is an excellent host for spin qubits that operate even above 4 K [Camenzind et al., arXiv:2103.07369; Geyer et al., APL 118, 104004 (2021)]. We achieve fast all-electrical control of hole spins through electric dipole spin resonance with driving frequencies up to 150 MHz and single-qubit gate fidelities at the fault-tolerance threshold. Our Rabi oscillation quality factor already matches or exceeds the reported values for other hole spin qubits at mK temperatures. In addition, charge sensing in FinFETs and the feasibility of single-shot hole spin readout at few-kelvin temperatures will be discussed.