Two-level system loss and noise, and development of superconducting integrated quantum processors

We will show recent quantum hardware developments at Chalmers – materials, fabrication, design, and quantum algorithm implementations.

This includes a thorough characterization of fluctuations of dielectric loss and noise, due to temporal instability of individual two-level-system fluctuators, which represents an important relaxation and dephasing mechanism for superconducting qubits [1-3].

We have also implemented small-scale quantum algorithms, including the first enhancement of the fidelity of a QAOA solution by iterating the circuit to level two [4], and the demonstration of 3-qubit entangled states by implementing a novel 3-qubit gate in one single operation [5-6].

Finally, we have recently demonstrated scalable flip-chip modules, consisting of coupled transmon circuits, with relaxation times exceeding 100 us and with high gate fidelities [7]. We will show some design and processing steps that enabled these results [8-9].

[1] Burnett npjQI 5, 54 (2019)

[2] Niepce SUST 33, 025013 (2020)

[3] Niepce Sci. Adv. 7, eabh0462 (2021)

[4] PRAppl 14, 034010 (2020)

[5] Gu PRXQ 2, 040348 (2021)

[6] Warren preprint (2022)

[7] Kosen arXiv:2112.02717 (2021)

[8] Osman APL 118, 064002 (2021)

[9] Grigoras preprint (2022)