Robust Quantum Circuit Approximation for Resource-Efficient Circuit Synthesis
ORAL
Abstract
We present a procedure to robustly generate approximations for quantum circuits to reduce their CNOT gate count. Our approach employs circuit partitioning for scalability with procedures to 1) reduce circuit length using approximate synthesis, 2) improve fidelity by running circuits that represent key samples in the approximation space, and 3) reason about approximation upper bound. Our evaluation results indicate that our approach of "dissimilar" approximations provides close fidelity to the original circuit. Overall, the results indicate that the procedure can reduce CNOT gate count by 30-80% on ideal systems and decrease the impact of noise on existing and near-future quantum systems.
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Publication: Patel, Tirthak, Ed Younis, Costin Iancu, Wibe de Jong, and Devesh Tiwari. "Robust and Resource-Efficient Quantum Circuit Approximation." arXiv preprint arXiv:2108.12714 (2021).
Presenters
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Tirthak Patel
Northeastern University
Authors
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Tirthak Patel
Northeastern University
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Ed Younis
University of California, Berkeley
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Costin C Iancu
Lawrence Berkeley National Laboratory
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Bert A de Jong
Lawrence Berkeley National Laboratory, LBNL
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Devesh Tiwari
Northeastern University